1. Field of the Invention
The present invention relates to an under voltage lock out technique of monitoring the input voltage and preventing malfunction of circuits and devices in an under voltage condition.
2. Description of the Related Art
A great number of electronic circuits such as CPU (Central Processing Unit) and other DSP (Digital Signal Processor) which perform digital signal processing, liquid crystal panel and other analog circuits are mounted on recent various electronic equipments such as a mobile phone, a PDA (Personal Digital Assistant), a laptop computer and the like. The electronic circuits operate with power supplied from a battery or a power supply circuit for stabilizing the battery voltage.
A stable operation guaranteed voltage is defined for each electronic circuit, and the relevant electronic circuit does not operate properly if the supplied voltage is lower than the stable operation guaranteed voltage. Therefore, an under voltage lock out (hereinafter referred to as UVLO) function of monitoring the battery voltage and the like and controlling the start-up and terminating sequences of each electronic circuit is installed in such electronic equipment. Related arts are disclosed in Japanese Patent Application Laid-open Nos. 2004-22947 and 2004-126922 and the like.    [Patent Document 1] Japanese Patent Application Laid-open No. 2004-22947    [Patent Document 2] Japanese Patent Application Laid-open No. 2004-126922
The UVLO circuit compares the voltage to be monitored (hereinafter also referred to as monitored voltage) such as the battery voltage with a predetermined threshold voltage, executes a predetermined start-up sequence when the battery voltage becomes higher than a threshold voltage, and executes a predetermined terminating sequence when the battery voltage becomes lower than the threshold voltage. Japanese Patent Application Laid-open No. 2004-22947 discloses a technique of providing hysteresis characteristic to the threshold voltage, thereby the circuit is started up when the monitored voltage becomes equal to or higher than a predetermined value, and is stopped when the monitored voltage becomes a minimum value of the hysteresis characteristic.
The inventors have reviewed the conventional UVLO circuit having hysteresis characteristic and have come to realize the following problems.
FIG. 1 is a time chart for describing the problems of the UVLO circuit having hysteresis characteristic. FIG. 1 shows a battery voltage (monitored voltage) Vbat, a threshold voltage Vth, a UVLO signal S_UVLO representing the determination result on whether or not the battery voltage satisfies a predetermined level, and a power ON signal PWR_ON (hereinafter also referred to as start-up signal) from the outside, in this order from the top. The vertical axis and the horizontal axis of FIG. 1 and FIG. 4, to be hereinafter described, are appropriately enlarged or reduced for easier understanding, and each illustrated waveform is also simplified for the sake of facilitating the understanding.
The battery voltage Vbat gradually rises while charging and drops as the load is driven consuming the power. The battery voltage Vbat is compared with the threshold voltage Vth, and the comparison result is generated as the UVLO signal S_UVLO signal. In FIG. 1, the UVLO signal S_UVLO becomes high level when Vbat>Vth is satisfied.
The threshold voltage Vth has hysteresis characteristic in which the value changes according to the logic value of the UVLO signal S_UVLO, where the threshold voltage Vth is set to a first voltage value Vth1 when the UVLO signal S_UVLO is high level and the threshold voltage Vth is set to a second voltage value Vth2 when the UVLO signal S_UVLO is low level. The first voltage value Vthl is set to a lower limit of a voltage range in which a circuit controlled by the UVLO circuit can transit from a non-start-up state to a start-upstate. The second voltage value Vth2 is set corresponding to a lower limit of a voltage range in which the circuit cannot transit from the non-start-up state to the start-up state, but can operate.
The UVLO circuit executes a predetermined start-up sequence when the start-up signal PWR_ON becomes high level in a state where the UVLO signal S_UVLO is high level, that is, in a state where the battery voltage Vbat is higher than the threshold voltage.
The threshold voltage Vth is set to the first voltage value Vth1 before time t0. As the battery voltage Vbat rises through charging and becomes to satisfy Vbat>Vth1 at time t0, the UVLO signal S_UVLO becomes high level, and the threshold voltage Vth transits to the second voltage value Vth2. When the start-up signal PWR_ON instructing the start-up of the electronic equipment becomes high level while the UVLO signal S_UVLO is high level, the UVLO circuit executes a predefined sequence to operate the electronic equipment (time t1), so that the electronic equipment is in the operating state. This is the normal start-up sequence. Thereafter, when the start-up signal PWR_ON becomes low level the UVLO circuit executes a predetermined terminating sequence.
Assume a case in which the battery voltage Vbat drops to a voltage between the first voltage value Vth1 and the second voltage value Vth2 through discharge, as shown in time t3 to t4. The UVLO circuit triggers a problem in such case. The UVLO signal S_UVLO is maintained at high level until the battery voltage Vbat drops to the second voltage value Vth2. Therefore, the threshold voltage Vth is also maintained at the second voltage value Vth2.
In the above-described state, when the start-up signal PWR_ON becomes high level and start-up is instructed at time t5, the UVLO circuit executes the predetermined start-up sequence. However, even if the start-up sequence is executed, the load circuits such as CPU may not be started up and may not operate correctly since the battery voltage Vbat is lower than the first voltage value Vth1.